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| rev. prf (6/04 ) information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices.trademarks and registered tradermarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: ht tp://www.analog.com fax: 781/326-8703 analog devices, inc., 2004 3msps,12-/10-/8-bit adcs in 6-lead tsot preliminary technical data ad7276/ad7277/ad7278 preliminary technical data functional block diagram features fast throughput rate: 3msps specified for v dd of 2.35 v to 3.6v low power: 13.5 mw max at 3msps with 3v supplies tbd mw typ at 1.5msps with 3v supplies wide input bandwidth: 70db snr at 1mhz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface spi tm /qspi tm /microwire tm /dsp compatible power down mode: 1a max 6-lead tsot package 8-lead msop package ad7476 and ad7476a pin compatible applications battery-powered systems personal digital assistants medical instruments mobile communications instrumentation and control systems data acquisition systems high-speed modems optical sensors product highlights 1. 3msps adcs in a 6-lead tsot package. 2. ad7476/77/78 and ad7476a/77a/78a pin compatible. 3. high throughput with low power consumption. 4. flexible power/serial clock speed management. the conversion rate is determined by the serial clock allowing the conversion time to be reduced through the serial clock speed increase. this allows the average power consumption to be reduced when a power-down mode is used while not converting. the part also features a power-down mode to maximize power effi- ciency at lower throughput rates. current consumption is 1 a max when in power-down mode. 5. reference derived from the power supply. 6. no pipeline delay. the parts feature a standard successive-approximation adc with accurate control of the sampling instant via a input and once-off conversion control. general description the ad7276/ad7277/ad7278 are 12-bit, 10-bit and 8- bit, high speed, low power, successive-approximation adcs respectively. the parts operate from a single 2.35v to 3.6 v power supply and feature throughput rates up to 3 msps. the parts contain a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of tbd mhz. the conversion process and data acquisition are controlled using and the serial clock, allowing the devices to interface with microprocessors or dsps. the input signal is sampled on the falling edge of and the conversion is also initiated at this point. there are no pipeline delays associated with the part. the ad7276/ad7277/ad7278 use advanced design techniques to achieve very low power dissipation at high throughput rates. the reference for the part is taken internally from v dd. this allows the widest dynamic input range to the adc. thus the analog input range for the part is 0 to v dd . the conversion rate is determined by the sclk. t/h 8-/10-/12-bit successive approximation adc control logic v dd v in gnd sclk sdata &6 ad7276/ad7277/ad7278
?2? rev. prf preliminary technical data parameter b grade 1 units test conditions/comments dynamic performance f in = 1mhz sine wave signal-to-noise + distortion (sinad) 2 49 db min total harmonic distortion (thd) 2 -65 db max peak harmonic or spurious noise (sfdr) 2 -65 db max intermodulation distortion (imd) 2 second order terms -76 db typ fa= tbd khz, fb= tbd khz third order terms -76 db typ fa= tbd khz, fb= tbd khz aperture delay tbd ns typ aperture jitter tbd ps typ full power bandwidth tbd mhz typ @ 3 db full power bandwidth tbd mhz typ @ 0.1db dc accuracy resolution 8 bits integral nonlinearity 2 0.3 lsb max differential nonlinearity 2 0.3 lsb max guaranteed no missed codes to 8 bits offset error 2 0.5 lsb max tbd lsb typ gain error 2 0.5 lsb max tbd lsb typ total unadjusted error (tue) 2 tbd lsb max analog input input voltage ranges 0 to v dd volts dc leakage current 0.5 a max input capacitance tbd pf typ logic inputs input high voltage, v inh 0.7(v dd ) v min 2.35v vdd 2.7v 2 v min 2.7v < vdd 3.6v input low voltage, v inl 0.2(v dd ) v max 2.35v vdd< 2.7v 0.8 v max 2.7v vdd 3.6v input current, i in , sclk pin 0.5 a max typically tbd na, v in = 0 v or v dd input current, i in , pin tbd a max input capacitance, c in 3 10 pf max logic outputs output high voltage, v oh v dd - 0.2 v min i source = 200 a,v dd = 2.35 v to 3.6v output low voltage, v ol 0.2 v max i sink = 200a floating-state leakage current 1 a max floating-state output capacitance 3 10 pf max output coding straight (natural) binary conversion rate conversion time 192 ns max 10 sclk cycles with sclk at 52 mhz track/hold acquisition time 2 50 ns max throughput rate 3 m sps max power requirements v dd 2.35/3.6 vmin/max i dd digital i/ps= 0v or v dd normal mode(static) 2.5 ma typ v dd = 2.35v to 3.6v, sclk on or off normal mode (operational) 4.5 ma max v dd = 2.35v to 3.6v, f sample = 3msps full power-down mode (static) 1 a max sclk on or off, typically tbd na full power-down mode (dynamic) t b d ma typ v dd = 3v, f sample = 1msps power dissipation 4 normal mode (operational) 13.5 mw max v dd = 3v, f sample = 3msps full power-down 3 w max v dd = 3v ad7278-specifications ( v dd =+2.35 v to +3.6 v, f sclk =52 mhz, f sample =3 msps unless otherwise noted; t a =t min to t max , unless otherwise noted.) notes 1 temperature range from ?40c to +85c. 2 see terminology. 3 guaranteed by characterization. 4 see power versus throughput rate section. specifications subject to change without notice. ?3? rev. prf preliminary technical data parameter b grade 1 units test conditions/comments dynamic performance f in = 1 mhz sine wave signal-to-noise + distortion (sinad) 2 61 db min total harmonic distortion (thd) 2 -73 db max peak harmonic or spurious noise (sfdr) 2 -74 db max intermodulation distortion (imd) 2 second order terms -82 db typ fa= tbd khz, fb= tbd khz third order terms -82 db typ fa= tbd khz, fb= tbd khz aperture delay tbd ns typ aperture jitter tbd ps typ full power bandwidth tbd mhz typ @ 3 db full power bandwidth tbd mhz typ @ 0.1db dc accuracy resolution 10 bits integral nonlinearity 2 0.5 lsb max differential nonlinearity 2 0.5 lsb max guaranteed no missed codes to 10 bits offset error 2 1 lsb max tbd lsb typ gain error 2 1 lsb max tbd lsb typ total unadjusted error (tue) 2 tbd lsb max analog input input voltage ranges 0 to v dd volts dc leakage current 0.5 a max input capacitance tbd pf typ logic inputs input high voltage, v inh 0.7(v dd ) v min 2.35v vdd 2.7v 2 v min 2.7v ?5? rev. prf preliminary technical data preliminary technical data ad7276/ad7277/ad7278 limit at t min , t max parameter ad7276/ad7277/ad7278 units description f sclk 2 20 khz min 3 52 mhz max t convert 14 x t sclk ad7276 12 x t sclk ad7277 10 x t sclk ad7278 t quiet tbd ns min minimum quiet time required between bus relinquish and start of next conversion t 1 10 ns min minimum pulse width t 2 t b d ns min to sclk setup time t 3 4 tbd ns max delay from until sdata three-state disabled t 4 4 t b d ns max data access time after sclk falling edge t 5 0.4t sclk ns min sclk low pulse width t 6 0.4t sclk ns min sclk high pulse width t 7 4 t b d ns min sclk to data valid hold time t 8 5 tbd ns max sclk falling edge to sdata three-state tbd ns min sclk falling edge to sdata three-state t power-up 6 tbd s max power up time from full power-down notes 1 guaranteed by characterization. all input signals are specified with tr=tf=5ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 volts. 2 mark/space ratio for the sclk input is 40/60 to 60/40. 3 minimum f sclk at which specifications are guaranteed. 4 measured with the load circuit of figure 1 and defined as the time required for the output to cross the vih or vil voltage. 5 t 8 is derived form the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6 see power-up time section. specifications subject to change without notice. timing specifications 1 ( v dd = +2.35 v to +3.6 v; t a = t min to t max , unless otherwise noted.) figure 1. load circuit for digital output timing specifications +1.6v i ol 200a 200a i oh to output pin c l 25pf v ih v il t 7 sclk sdata v ih v il t 4 sclk sdata 1.4 v t 8 sclk sdata figure 2. access time after sclk falling edge figure 3. hold time after sclk falling edge figure 4. sclk falling edge to sdata three-state ? 6 ? rev. prf preliminary technical data ad7276/ad7277/ad7278 preliminary technical data figure 5. ad7276 serial interface timing diagram timing example 1 from figure 6, having f sclk = 52 mhz and a throughput of 3msps, gives a cycle time of t 2 + 12.5(1/f sclk ) + t acq = 333 ns. with t 2 = tbd ns min, this leaves t acq to be tbd ns. this tbd ns satisfies the requirement of tbd ns for t acq . figure 6 shows that, t acq comprises of 2.5(1/f sclk ) + t 8 + t quiet , where t 8 = tbd ns max. this allows a value of tbd ns for t quiet satisfying the minimum requirement of tbd ns. timing example 2 having f sclk = 20 mhz and a throughput of 1.5 msps, gives a cycle time of t 2 + 12.5(1/f sclk ) + t acq = 666 ns. with t 2 = tbd ns min, this leaves t acq to be tbd ns. this tbd ns satisfies the requirement of tbd ns for t acq . from figure 6, t acq comprises of 2.5(1/f sclk ) + t 8 + t quiet , where t 8 = tbd ns max. this allows a values of tbd ns for t quiet satisfying the minimum requirement of tbd ns. figure 6. serial interface timing example figures 5 and 6 show some of the timing parameters from the timing specifications table. &6 sclk 151315 sdata 2 leading zero?s three- state t 4 2 3 4 16 t 5 t 3 t quiet t convert t 2 three-state db 1 0 t 6 t 7 t 8 14 zero z b t 1 1/ throughput db11 db9 zero zero db 0 db1 2 trailing zero?s sclk 1 5 2 34 &6 13 t qu iet t 2 t 8 14 b t acquisition 12.5(1/fsclk) 1/throughput t convert t 1 15 16 12 ? 7 ? rev. prf preliminary technical data preliminary technical data ad7276/ad7277/ad7278 absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to gnd......................................-0.3 v to tbd v analog input voltage to gnd......?0.3 v to v dd + 0.3 v digital input voltage to gnd..............?0.3 v to tbd v digital output voltage to gnd....?0.3 v to v dd + 0.3 v input current to any pin except supplies 2 ..........10 ma operating temperature range commercial (b grade)......................?40c to +85c storage temperature range..............?65c to +150c junction temperature..........................................150c 6-lead tsot package ja thermal impedance........................ ..........tbd c/w jc thermal impedance ....................... .........tbdc/w notes 1 stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up. 8-lead msop package ja thermal impedance........................ .........205.9 c/w jc thermal impedance ....................... ........ 43.74c/w lead temperature soldering reflow (10- 30 sec) ...................................+tbdc esd................................................................. tbd kv lead tsot pin configuration ad7276/ad7277/ad7278 ordering guide temperature linearity package package branding model range error (lsb) 1 option description information ad7276buj-reel ?40c to +85c 1 max uj-6 tsot tbd ad7276brm ?40c to +85c 1 max rm-8 msop tbd ad7277buj-reel ?40c to +85c 0.5 max uj-6 tsot tbd ad7277brm ?40c to +85c 0.5 max rm-8 msop tbd ad7278buj-reel ?40c to +85c 0.3 max uj-6 tsot tbd AD7278BRMJ ?40c to +85c 0.3 max rm-8 msop tbd notes 1 linearity error here refers to integral nonlinearity. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7276/ad7277/ad7278 feature proprietary esd protection circuitry, perma- nent damage may occur on devices subjected to high energy electrostatic discharges. there- fore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. &6 sdata sclk v in v dd gnd top view 1 2 3 4 5 6 (not to scale) ad7276/ ad7277/ ad7278 top view 1 2 3 4 5 6 &6 sdata sclk v in (not to scale) v dd gnd ad7276/ ad7277/ ad7278 7 8 nc nc 8-lead msop ? 8 ? rev. prf preliminary technical data ad7276/ad7277/ad7278 preliminary technical data pin function description pin mnemonic function chip select. active low logic input. this input provides the dual function of initiating conversion on the ad7276/ad7277/ad7278 and also frames the serial data transfer. v dd power supply input. the v dd range for the ad7276/ad7277/ad7278 is from +2.35v to +3.6v. g n d analog ground. ground reference point for all circuitry on the ad7276/ad7277/ad7278. all analog input signals should be referred to this gnd voltage. v in analog input. single-ended analog input channel. the input range is 0 to v dd . sdata d ata out. logic output. the conversion result from the ad7276/ad7277/ad7278 is pro- vided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream from the ad7276 consists of two leading zeros followed by the 12 bits of conversion data followed by two trailing zeros, which is provided msb first. the data stream from the ad7277 consists of two leading zeros followed by the 10 bits of conversion data followed by four trailing zeros, which is provided msb first. the data stream from the ad7278 consists of two leading zeros followed by the 8 bits of conversion data followed by six trailing zeros, which is provided msb first. sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the ad7276/ad7277/ad7278's conver- sion process. ? 9 ? rev. prf preliminary technical data preliminary technical data ad7276/ad7277/ad7278 thd (db ) 20 log v 2 2 v 3 2 v 4 2 v 5 2 v 6 2 v 1 terminology integral nonlinearity this is the maximum deviation from a straight line pass- ing through the endpoints of the adc transfer function. for the ad7276/ad7277/ad7278, the endpoints of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e, agnd + 0.5 lsb . gain error this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal, i.e, v ref ? 1.5lsb after the offset error has been adjusted out. total unadjusted error this is a comprehensive specification which includes gain, linearity and offset errors. track/hold acquisition time the track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 0.5 lsb, after the end of conversion. see serial interface section for more details. signal to noise ratio (snr) this is the measured ratio of signal to noise at the output to the a/d converter. the signal is the rms value of the sine wave input. noise is the rms quantization error within the nyquist bandwitdh (fs/2). the rms value of a sine wave is one half its peak to peak value divided by 2 and the rms value for the quantization noise is q/ 12. the ratio is dependant on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. for an ideal n-bit converter, the snr is defined as: snr = 6.02 n + 1.76 db thus for a 12-bit converter this is 74 db, for a 10-bit converter it is 62db and for an 8-bit converter it is 50db. practically, though, various error sources in the adc cause the measured snr to be less than the theoretical value. these errors occur due to integral and differential nonlinearities, internal ac noise sources, etc. signal-to- (noise + distortion) ratio (sinad) this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms value of the sine wave and noise is the rms sum of all nonfundamentals signals up to half the sampling frequency (fs/2), including harmonics but excluding dc. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. it is defined as: where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms in- clude (fa + fb) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb). the ad7276/ad7277/ad7278 are tested using the ccif standard where two input frequencies are used (see fa and fb in the specification page). in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. aperture delay this is the measured interval between the leading edge of the sampling clock and the point at which the adc actually takes the sample. aperture jitter this is the sample-to-sample variation in the effective point in time at which the sample is taken. ? 10 ? rev. prf preliminary technical data ad7276/ad7277/ad7278 preliminary technical data performance curves dynamic performance curves tpc 1, tpc 2 and tpc 3 show typical fft plots for the ad7276, ad7277 and ad7278 respectively, at 3 msps sample rate and tbd khz input tone. tpc 4 shows the signal-to-(noise+distortion) ratio performance versus input frequency for various supply voltages while sampling at 3 msps with a sclk frequency of 52 mhz for the ad7276. tpc 5 shows the signal to noise ratio (snr) performance versus input frequency for various supply voltages while sampling at 3 msps with a sclk frequency of 52 mhz for the ad7276. tpc 6 shows a graph of the total harmonic distortion versus analog input signal frequency for various supply voltages while sampling at 3 msps with a sclk frequency of 52 mhz for the ad7276. tpc 7 shows a graph of the total harmonic distortion versus analog input frequency for different source impedances when using a supply voltage of tbd v, sclk frequency of 52 mhz and sampling at a rate of 3 msps for the ad7276. see analog input section. dc accuracy curves tpc 8 and tpc 9 show typical inl and dnl performance for the ad7276. power requirements curves tpc10 shows maximum current versus supply voltage for the ad7276 with different sclk frequencies. see also power versus throughput rate section. typical performance characteristics tpc 1. ad7276 dynamic performance at 3 msps tpc 2. ad7277 dynamic performance at 3 msps title 0 0 t i t l e tbd title 0 0 t i t l e tbd ? 11 ? rev. prf preliminary technical data preliminary technical data ad7276/ad7277/ad7278 tpc 8. ad7276 inl performance tpc 5. ad7276 snr vs analog input frequency at 3 msps for various supply voltages tpc 3. ad7278 dynamic performance at 3 msps tpc 6. thd vs. analog input frequency at 3 msps for various supply voltages title 0 0 t i t l e tbd tpc 7. thd vs. analog input frequency for various source impedance title 0 0 t i t l e tbd title 0 0 t i t l e tbd title 0 0 t i t l e tbd title 0 0 t i t l e tbd title 0 0 t i t l e tbd tpc 4. ad7276 sinad vs analog input frequency at 3 msps for various supply voltages ? 12 ? rev. prf preliminary technical data ad7276/ad7277/ad7278 preliminary technical data tpc 10. maximum current vs supply voltage for different sclk frequencies. tpc 9. ad7276 dnl performance title 0 0 t i t l e tbd title 0 0 t i t l e tbd ? 13 ? rev. prf preliminary technical data preliminary technical data ad7276/ad7277/ad7278 circuit information the ad7276/ad7277/ad7278 are fast, micropower, 12-/ 10-/8-bit, single supply, a/d converters respectively. the parts can be operated from a +2.35v to +3.6v supply. when operated from any supply voltage within this range, the ad7276/ad7277/ad7278 are capable of throughput rates of 3 msps when provided with a 52 mhz clock. the ad7276/ad7277/ad7278 provide the user with an on-chip track/hold, a/d converter, and a serial interface housed in a tiny 6-lead tsot or 8-lead msop package, which offers the user considerable space saving advantages over alternative solutions. the serial clock input accesses data from the part but also provides the clock source for the successive-approximation a/d converter. the analog input range is 0 to v dd . an external reference is not required for the adc and neither is there a reference on- chip. the reference for the ad7276/ad7277/ad7278 is derived from the power supply and thus gives the widest dynamic input range. the ad7276/ad7277/ad7278 also feature a power down option to allow power saving between conversions. the power-down feature is implemented across the standard serial interface as described in the modes of operation section. converter operation the ad7276/ad7277/ad7278 is a successive- approximation analog-to-digital converter based around a charge redistribution dac. figures 7 and 8 show simplified schematics of the adc. figure 7 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition and the sampling capacitor acquires the signal on v in . when the adc starts a conversion, see figure 8, sw2 will open and sw1 will move to position b causing the comparator to become unbalanced. the control logic and the charge redistribution dac are used to add and subtract fixed amounts of charge from the sampling ca- pacitor to bring the comparator back into a balanced con- dition. when the comparator is rebalanced the conversion is complete. the control logic generates the adc out- put code. figure 9 shows the adc transfer function. figure 7. adc acquisition phase charge redistribution dac v in v dd / 2 sampling capacitor comparator control logic acquisition phase sw1 a b sw2 agnd adc transfer function the output coding of the ad7276/ad7277/ad7278 is straight binary. the designed code transitions occur midway between succesive integer lsb values, i.e, 0.5lsb, 1.5lsbs, etc. the lsb size is v dd /4096 for the ad7276, v dd /1024 for the ad7277 and v dd /256 for the ad7278. the ideal transfer characteristic for the ad7276/ ad7277/ad7278 is shown in figure 9. figure 8. adc conversion phase charge redistribution dac v in v dd / 2 sampling capacitor comparator control logic conversion phase sw1 a b sw2 agnd figure 9. ad7276/ad7277/ad7278 transfer characteristic 000...000 0v a d c c o d e analog input 111...111 000...001 000...010 111...110 111...000 011...111 0.5lsb +v dd -1.5lsb 1lsb = v dd /1024 (ad7277) 1lsb = v dd /256 (ad7278) 1lsb = v dd /4096 (ad7276) ? 14 ? rev. prf preliminary technical data ad7276/ad7277/ad7278 preliminary technical data typical connection diagram figure 10 shows a typical connection diagram for the ad7276/ad7277/ad7278. v ref is taken internally from v dd and as such v dd should be well decoupled. this provides an analog input range of 0v to v dd . the conversion result is output in a 16-bit word with two leading zeros followed by the 12-bit, 10-bit or 8-bit result. the 12-bit result from the ad7276 will be followed by two trailing zeros and the 10-bit and 8-bit result from the ad7277 and ad7278 will be followed by four and six trailing zeros respectively. alternatively, because the supply current required by the ad7276/ad7277/ad7278 is so low, a presision reference can be used as the supply source to the ad7276/ad7277/ ad7278. a ref19x voltage reference (ref193 for 3v) can be used to supply the required voltage to the adc -see figure 10. this configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 3v (e.g. 5v or 15v). the ref19x will output a steady voltage to the ad7276/ 7277/7278. if the low dropout ref193 is used, the current it needs to supply to the ad7276/ad7277/ ad7278 is typically tbd ma. when the adc is converting at a rate of 3 msps the ref193 will need to supply a maximum of tbd ma to the ad7276/ad7277/ ad7278. the load regulation of the ref193 is typically 10 ppm/ma (ref193, v s = 5v), which results in an error of tbd ppm (tbd v) for the tbd ma drawn from it. this corresponds to a tbd lsb error for the ad7276 with v dd = 3v from the ref193, a tbd lsb error for the ad7277, and a tbd lsb error for the ad7278. for applications where power consumption is of concern, the power-down mode of the adc and the sleep mode of the ref19x reference should be used to improve power per- formance. see modes of operation section. figure 10. ref193 as power supply to ad7276/ ad7277/ad7278 v dd v in gnd +5v supply 0.1 f 10f ref193 0.1f 1f tant +3v 0v tov dd input sdata dsp/ c/p sclk serial interface &6 tbd ma 680nf ad7276/ ad7277/ ad7278 table i provides some typical performance data with various references used as a v dd source under the same set-up conditions. reference tied ad7276 snr performance to v dd tbd khz input ad780@3v tbd db adr423 tbd db ad780@2.5v tbd db ref192 tbd db adr421 tbd db adr291 tbd db table i. ad7276 performance for various voltage references ic analog input figure 11 shows an equivalent circuit of the analog input structure of the ad7276/ad7277/ad7278. the two diodes d1 and d2 provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300mv. this will cause these diodes to become forward biased and start conducting current into the substrate. 10ma is the maximum current these diodes can conduct without causing irreversable damage to the part. the capacitor c1 in figure 11 is typically about 4pf and can primarily be attributed to pin capacitance. the resistor r1 is a lumped component made up of the on resistance of a switch. this resistor is typically about tbd . the capacitor c2 is the adc sampling capacitor and has a capacitance of tbd pf typically. for ac applications, removing high frequency components from the analog input signal is recommended by use of a bandpass filter on the relevant analog input pin. in applications where harmonic distor- tion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac perfor- mance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op-amp will be a function of the particular application. figure 11. equivalent analog input circuit v in d1 v dd d2 r1 c2 tbd pf c1 4pf conversion phase - switch open track phase - switch closed ? 15 ? rev. prf preliminary technical data preliminary technical data ad7276/ad7277/ad7278 table ii provides some typical performance data with various op-amps used as the input buffer under the same set-up conditions. op-amp in the ad7276 snr performance input buffer tbd khz input ad8510 tbd db ad8610 tbd db ad8038 tbd db ad8519 tbd db when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases and performance will degrade. tpc 7 shows a graph of the total harmonic distortion versus analog input frequency for different source impedances when using a supply voltage of tbd v and sampling at a rate of 3 msps. table ii. ad7276 performance for various input buffers digital inputs the digital inputs applied to the ad7276/ad7277/ ad7278 are not limited by the maximum ratings which limit the analog inputs. instead, the digitals inputs applied can go to tbdv and are not restricted by the v dd + 0.3v limit as on the analog inputs. for example, if the ad7276/ad7277/ad7278 were operated with a v dd of 3v then 5v logic levels could be used on the digital inputs. however, it is important to note that the data output on sdata will still have 3v logic levels when v dd = 3v. another advantage of sclk and not being restricted by the v dd + 0.3v limit is the fact that power supply sequencing issues are avoided. if or sclk are applied before v dd then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3v was applied prior to v dd . modes of operation the mode of operation of the ad7276/ad7277/ad7278 is selected by controlling the logic state of the signal during a conversion. there are two possible modes of operation, normal mode and power-down mode. the point at which is pulled high after the conversion has been initiated will determine whether the ad7276/ ad7277/ad7278 will enter power-down mode or not. similarly, if already in power-down then can control whether the device will return to normal operation or remain in power-down. these modes of operation are designed to provide flexible power management options. these options can be chosen to optimize the power dissi- pation/throughput rate ratio for different application requirements. normal mode this mode is intended for fastest throughput rate perfor- mance as the user does not have to worry about any power-up times with the ad7276/ad7277/ad7278 remaining fully powered all the time. figure 12 shows the general diagram of the operation of the ad7276/ad7277/ ad7278 in this mode. the conversion is iniated on the falling edge of as described in the serial interface section. to ensure the part remains fully powered up at all times must remain low until at least 10 sclk falling edges have elapsed after the falling edge of . if is brought high any time after the 10th sclk falling, the part will remain powered up but the conversion will be terminated and sdata will go back into three-state. for the ad7276 a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result. for the ad7277 and ad7278 a minimum of 12 and 10 serial clock cycles are required to complete the conversion and access the complete con- version result, respectively. may idle high until the next conversion or may idle low until returns high sometime prior to the next conversion (effectively idling low). once a data transfer is complete (sdata has returned to three-state), another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing low again. figure 12. normal mode operation 12 14 16 ad7276/77/78 va l i d d ata sdata sclk &6 1 10 ? 16 ? rev. prf preliminary technical data ad7276/ad7277/ad7278 preliminary technical data figure 13. entering power down mode figure 14. exiting power down mode three-state 1 16 10 2 sdata sclk & 6 invalid data sclk &6 invalid data valid data 1 10 16 16 1 th e pa rt b egi ns to power up thepartisfully poweredupwithv in fully acquired a sdata power-down mode this mode is intended for use in applications where slower throughput rates are required; either the adc is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and then the adc is powered down for a relatively long duration between these bursts of several conversions. when the ad7276/ad7277/ad7278 is in power-down, all analog circuitry is powered down. to enter power-down, the conversion process must be interrupted by bringing high anywhere after the second falling edge of sclk and before the 10th falling edge of sclk as shown in figure 13. once has been brought high in this window of sclks, then the part will enter power-down and the conversion that was intiated by the falling edge of will be terminated and sdata will go back into three-state. if is brought high before the second sclk falling edge, then the part will remain in normal mode and will not power-down. this will avoid accidental power-down due to glitches on the line. in order to exit this mode of operation and power the ad7276/ad7277/ad7278 up again, a dummy conversion is performed. on the falling edge of the device will begin to power up, and will continue to power up as long as is held low until after the falling edge of the 10th sclk. the device will be fully powered up once 16 sclks have elapsed and valid data will result from the next conversion as shown in figure 14. if is brought high before the 10th falling edge of sclk, then the ad7276/ad7277/ad7278 will go back into power- down again. this avoids accidental power up due to glitches on the line or an inadvertent burst of 8 sclk cycles while is low. so, although the device may begin to power up on the falling edge of , it will power down again on the rising edge of as long as it occurs before the 10th sclk falling edge. ? 17 ? rev. prf preliminary technical data preliminary technical data ad7276/ad7277/ad7278 power-up time the power-up time of the ad7276/ad7277/ad7278 is tbd ns, which means that with any frequency of sclk up to 52 mhz, one dummy cycle will always be sufficient to allow the device to power up. once the dummy cycle is complete, the adc will be fully powered up and the input signal will be acquired properly. the quite time t quiet must still be allowed from the point where the bus goes back into three-state after the dummy conversion, to the next falling edge of . when running at 3 msps throughput rate, the ad7276/ad7277/ad7278 will power up and acquire a signal within 0.5lsb in one dummy cycle, i.e. tbd ns. when powering up from the power-down mode with a dummy cycle, as in figure 14, the track and hold which was in hold mode while the part was powered down, returns to track mode after the first sclk edge the part receives after the falling edge of . this is shown as point a in figure 14. although at any sclk frequency one dummy cycle is sufficient to power the device up and acquire v in , it does not necessarily mean that a full dummy cycle of 16 sclks must always elapse to power up the device and acquire v in fully; tbd ns will be suffi- cient to power the device up and acquire the input signal. if, for example, a 25 mhz sclk frequency was applied to the adc, the cycle time would be 640 ns. in one dummy cycle, 640 ns, the part would be powered up and v in acquired fully. however after tbd ns with a 25 mhz sclk only tbd sclk cycles would have elapsed. at this stage, the adc would be fully powered up and the signal acquired. so, in this case the can be brought high after the 10th sclk falling edge and brought low again after a time t quiet to initiate the conversion. when power supplies are first applied to the ad7276/ ad7277/ad7278, the adc may either power up in the power-down mode or in normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. likewise, if it is intended to keep the part in the power-down mode while not in use and the user wishes the part to power up in power-down mode, then the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as that shown in figure 13. once supplies are applied to the ad7276/ ad7277/ad7278, the power up time is the same as that when powering up from the power-down mode. it takes approximately tbd ns to power up fully if the part powers up in normal mode. it is not necessary to wait tbd ns before executing a dummy cycle to ensure the desired mode of operation. instead, the dummy cycle can occur directly after power is supplied to the adc. if the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. as mentioned earlier, when powering up from the power-down mode, the part will return to track upon the first sclk edge applied after the falling edge of . however, when the adc powers up initially after supplies are applied, the track and hold will already be in track. this means, assuming one has the facility to monitor the adc supply current, if the adc powers up in the desired mode of operation and thus a dummy cycle is not required to change mode, then neither is a dummy cycle required to place the track and hold into track. power versus throughput rate by using the power-down mode on the ad7276/ad7277/ ad7278 when not converting, the average power con- sumption of the adc decreases at lower throughput rates. figure 15 shows how as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption over time drops accordingly. for example, if the ad7276/ad7277/ad7278 is operated in a continuous sampling mode with a throughput rate of 500ksps and a sclk of 52mhz (v dd = 3v), and the device is placed in the power-down mode between conversions, then the power consumption is calculated as follows. the power dissipation during normal operation is 13.5 mw (v dd = 3v). if the power up time is one dummy cycle, i.e. 333ns, and the remaining conversion time is another cycle, i.e. 333ns, then the ad7276/ad7277/ ad7278 can be said to dissipate 13.5mw for 666ns during each conversion cycle.if the throughput rate is 500ksps, the cycle time is 2 s and the average power dissipated during each cycle is (666/2000) x (13.5 mw)= 4.5mw. figure 15 shows the power vs. throughput rate when using the power-down mode between conversions at 3v. the power-down mode is intended for use with throughput rates of approximately tbd msps and under as at higher sampling rates there is no power saving made by using the power-down mode. title 0 0 t i t l e tbd figure 15. power vs throughput ? 18 ? rev. prf preliminary technical data ad7276/ad7277/ad7278 preliminary technical data serial interface figures 16, 17 and 18 show the detailed timing diagram for serial interfacing to the ad7276, ad7277 and ad7278 respectively. the serial clock provides the conversion clock and also controls the transfer of information from the ad7276/ad7277/ad7278 during conversion. the signal initiates the data transfer and conversion process. the falling edge of puts the track and hold into hold mode, takes the bus out of three-state and the analog input is sampled at this point. the conversion is also initiated at this point. for the ad7276 the conversion will require 14 sclk cycles to complete. once 13 sclk falling edges have elapsed the track and hold will go back into track on the next sclk rising edge as shown in figure 16 at point b. if the rising edge of occurs before 14 sclks have elapsed then the conversion will be terminated and the sdata line will go back into three-state. if 16 sclks are considered in the cycle, the last two bits will be zeros and sdata will return to three-state on the 16th sclk falling edge as shown in figure 16. for the ad7277 the conversion will require 12 sclk cycles to complete. once 11 sclk falling edges have elapsed, the track and hold will go back into track on the next sclk rising edge, as shown in figure 17 at point b. if the rising edge of occurs before 12 sclks have elapsed then the conversion will be terminated and the sdata line will go back into three-state. if 16 sclks are considered in the cycle, the ad7277 will clock out four trailing zeros for the last four bits and sdata will return to three-state on the 16th sclk falling edge, as shown in figure 17. for the ad7278 the conversion will require 10 sclk cycles to complete. once 9 sclk falling edges have figure 16. ad7276 serial interface timing diagram elapsed, the track and hold will go back into track on the next rising edge. if the rising edge of occurs before 10 sclks have elapsed then the part will enter power-down mode. if 16 sclks are considered in the cycle, the ad7278 will clock out six trailing zeros for the last six bits and sdata will return to three-state on the 16th sclk falling edge, as shown in figure 18. if the user considers a 14 sclks cycle serial interface for the ad7276/ad7277/ad7278, needs to be brought high after the 14th sclk falling edge, the last two trailing zeros will be ignored and sdata will go back into three-state. in this case, the 3msps throughput could be achieved using a 45mhz clock frequency. going low clocks out the first leading zero to be read in by the microcontroller or dsp. the remaining data is then clocked out by subsequent sclk falling edges beginning with the 2nd leading zero. thus the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. the final bit in the data transfer is valid on the 16th falling edge, having being clocked out on the previous (15th) falling edge. in applications with a slower sclk, it is possible to read in data on each sclk rising edge. in that case, the first falling edge of sclk will clock out the second leading zero and it could be read in the first rising edge. however, the first leading zero that was clocked out when went low will be missed unless it was not read in the first falling edge. the 15th falling edge of sclk will clock out the last bit and it could be read in the 15th rising sclk edge. if goes low just after one the sclk falling edge has elapsed, will clock out the first leading zero as before and it may be read in the sclk rising edge. the next sclk falling edge will clock out the second leading zero and it could be read in the following rising edge. &6 sclk 151315 sdata 2 leading zero ? s three- state t 4 234 16 t 5 t 3 t quiet t convert t 2 three-state db 1 0 t 6 t 7 t 8 14 zero z b t 1 1/ throughput db11 db9 zero zero db 0 db1 2trailing zero ? s ? 19 ? rev. prf preliminary technical data preliminary technical data ad7276/ad7277/ad7278 figure 18. ad7278 serial interface timing diagram &6 11 15 t 5 16 t quiet three-state t 8 14 zero zero 6trailing zero ? s zero b sclk 1 sdata 2 l ea di ng zero ? s three- state t 4 234 t 3 t convert t 2 db6 t 6 t 7 zero z t 1 1/ throughput db 7 db0 db1 8 9 10 figure 17. ad7277 serial interface timing diagram &6 13 1 5 t 5 16 t quiet three-state t 8 14 zero zero 4trailing zero ? s zero zero b sclk 1 sdata 2 le a di ng zero ? s three- state t 4 2 3 4 t 3 t convert t 2 db 8 t 6 t 7 zero z t 1 1/ throughput db9 db0 db1 10 11 12 ad7278 in a 10 sclk?s cycle serial interface for the ad7278, if is brought high in the 10th rising edge after the 2 leading zeros and the 8 bits of the conversion have been provided, the part can achieve a 4.2msps throughput rate. for the ad7278, the track and hold goes back into track in the 9th rising edge. in that case, a f sclk = 52 mhz and a throughput of 4.2msps, gives a cycle time of t 2 + 8.5(1/f sclk ) + t acq = 238ns. with t 2 = tbdns min, this leaves t acq to be tbdns. this tbdns satisfies the requirement of 50 ns for t acq . from figure 19, t acq comprises of 0.5(1/f sclk ) + t 8 + t quiet , where t 8 = tbdns max. this allows a value of tbdns for t quiet satisfying the minimum requirement of tbdns. figure 19. ad7278 in a 10 sclk cycle serial interface &6 sclk t 1 15 9 sdata 2 leading zero ? s 3-state 3- state db7 db6 db0 zero z db1 23 4 t quiet t convert t 2 t 6 t 8 10 b 1/ throughput t acq db5 8.5 (1/ fsclk) ? 20 ? rev. pra preliminary technical data preliminary technical data outline dimensions dimensions shown in millimeters 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 27 0.120 (3.05) 0.112 (2.84) compliant to jedec standards mo-187aa ad7276/ad7277/ad7278 1 3 4 5 2 6 pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.22 0.08 10 4 0 0.50 0.30 0.10 max 0.90 0.87 0.84 seating plane 1.00 max 0.60 0.45 0.30 2.90 bsc 6-lead thin small outline transistor package [tsot] (uj-6) dimensions shown in millimeters compliant to jedec standards mo-193aa |
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